The Industry's Only Fully-Integrated PCI Express Solution
Application Note
General Description of Power Management Features
SPX-APP-400-1
SPX Series of PCI Express™ Analyzers and Exercisers
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©2005 Catalyst Enterprises, Inc. All rights reserved. Information herein regarding technology, devices, and applications is intended to suggest possible uses and implementations and may be superseded.
Reference
Catalyst Enterprises internal document 400-0082-001
PCI Express is a trademark of the PCI Special Interest Group (SIG). All other trademarks are the property of their respective owners.
Introduction
The SPX Series of PCI Express™ analyzers and exercisers provide engineers with various tool sets considered instrumental in design verification, validation, debug, characterization, and analysis.
An important feature provided by both SPX analyzer and exerciser products is the ability to support testing for PCI Express power management states. These features include the ability to detect and trigger on an electrical idle state on the link, capture and characterize low power state entry and exit behaviors, and force an electrical idle state on the link.
Definition of Terms
Electrical Idle
The term electrical idle refers to the bus state at which a transmitter’s output lines (D+ and D-) are driven to the DC common mode voltage.
Logical Idle
A logical idle is defined as one or more symbol times during which no transaction layer packets (TLP), data link layer packets (DLLP), or special symbols are being transmitted or received. During this state, the idle character (00h) is transmitted.
Electrical Idle Ordered Set
An electrical idle ordered set is a 4-character primitive as described below. An electrical idle ordered set is used to signal transitions to and from various low power states.
K28.5 K28.3 K28.3 K28.3 (COM IDL IDL IDL)
Fast Training Sequence (FTS) Ordered Set
An FTS ordered set is used by a receiver to achieve bit and symbol lock during a transition from L0s to L0. During the link training process, devices advertise the number of FTS (N_FTS) ordered sets they require. The maximum number of FTS ordered sets that a device can request is 255. If the extended synch bit is set, 4096 FTS are delivered.
K28.5 K28.1 K28.1 K28.1 (COM FTS FTS FTS)
Active State Power Management (ASPM)
Refers to
power-savings protocols, self-managed by the hardware. There are
two low power states defined for ASPM, including L0s (L0 Standby)
and L1. See link state descriptions
below.
Link State Descriptions
Various link state descriptions pertinent to this document are described below as an aid in understanding SPX power management features and descriptions.
|
State |
Description |
|
L0 |
Normal operating state, where packets are transmitted and received. |
|
L0s |
Power savings state which allows for quick entry and exit back to L0 without having to go through link recovery. Entry to this state occurs after receipt of an electrical idle ordered set. Applies to a single link direction. |
|
L1 |
Optional power savings state which provides additional power savings as compared to L0s, but at the cost of increased state exit latency. L1 is entered after receipt of a special data link layer packet (DLLP) and an electrical idle ordered set. Applies to both directions on the link. |
|
|
|
|
|
Note: not all link states are listed here. |
Table 1. Link State Descriptions.
Power Management Support Provided by the SPX Exerciser
SPX Exerciser Overview
The SPX exerciser is a live, highly-controllable PCI Express engine with an integrated capture, trigger, and display capability. The exerciser operates as either an endpoint or as a root complex, and is able to link train at various widths, automatically operate necessary link activities at the physical layer (such as SKP ordered set generation) and data link layer (such as flow control updates), and execute specified traffic sequences at the transaction layer.
Traffic at all three layers may be precisely manipulated to control specific characteristics for testing purposes. The exerciser includes a concurrent ability to capture and display traffic that it sends and receives. This traffic is also subject to the standard trigger capabilities also found on the SPX analyzer.
Datasheets, software, and feature descriptions on the SPX Exerciser can be found at http://getcatalyst.com/product-pciexpress.html.
Figure 1. SPX-4 Analyzer/Exerciser
The SPX Exerciser may be installed in a PCI Express system slot or onto the PXP-100 development platform, shown below. Information on the PXP-100 development platform can be found at http://www.getcatalyst.com/pxp-100.html.
Figure 2. PXP-100 Development Platform.
Exerciser Power Management Settings Menu
Application software described below is available at http://getcatalyst.com/downloads.html.
The SPX Power Management Settings menu is located under:
Link Settings -> Advanced Options -> Power Management Settings
Figure 3. Power Management Settings Menu.
Disabled vs. L0s Enabled
The Power Management Support Level determines the support level for the exerciser’s transmitter. Options selectable here include Disabled and L0s Enabled.
L0s Entry Delay
When L0s Enabled is selected, the user is permitted to enter a value in the L0s Entry Delay box. This value controls the period of logical idle time the exerciser will tolerate before initiating entry to L0s. The bus is considered logically idle in the absence of TLP or DLLP activity (character 0x00 is transmitted during this time). SKP ordered sets are not considered as interruptive of this logical idle state. The L0s Entry Delay can be set between 0us and 255us. By default this value is set at 10us.
Important: Keep in mind that if this value is set too high, normal bus activity such as flow control updates, will prevent a timeout condition and therefore prevent the exerciser from entering L0s/electrical idle.
Number of FTS Ordered Sets Sent on L0s Exit
When the exerciser’s transmitter exits the L0s state to enter the L0 state, it will transmit a sequence of FTS ordered sets, which allow the link partner device to gain bit and symbol lock. The number of FTS ordered sets (N_FTS) to be sent are defined by the user as follows:
|
Mode |
Description |
|
Auto |
Sends the value advertised by the link partner device during link training
|
|
Manual |
User may select a value of FTS to send from 0 to 8191 (0x1FFF)
|
|
Max |
The extended synch value of 4096 FTS are sent
|
|
|
Note: FTS Ordered Sets transmitted from the Exerciser are within +2/-0 in x1 and +/- 0 in x4 of the requested value. |
Table 2. FTS Transmitter Options.
Altering the Advertised FTS Value Needed for the SPX Exerciser
The SPX exerciser, just like any other PCI Express device, will advertise an N_FTS value during link training. See figure 4 below. This value can be controlled by the user from 0 to 255 (0xFF). By default, this value is set to 255.
Note: The SPX requires a minimum value of 20 FTS to achieve proper bit and symbol lock.
This value is set in:
Link Settings -> Advanced Options -> Physical Layer Settings
Figure 4. N_FTS Setting.
Exerciser Receiver-Side Capabilities
The exerciser is capable of triggering on an electrical idle state, and displaying this state along with packet and logical idle activity associated with entry and exit to/from this state. The duration of the electrical idle event is displayed in the capture view as well.
The receive side of the exerciser typically requires a minimum of 20 FTS to ensure bit and symbol lock in x1 mode, and 30 in x4 mode.
Power Management Support for the SPX Analyzer
SPX Analyzer Overview
The SPX Analyzer is a passive instrument inserted between two communicating link partner devices, such as an endpoint and a root complex. All bus traffic between the two devices is tapped off into the analyzer’s recording engine. The analyzer includes filtering capabilities, and allows for both simple and complex trigger schemes to stop the capture sequence and subsequently display this traffic in intuitive packet and list view formats.
Datasheets, software, and feature descriptions on this product can be found at http://getcatalyst.com/product-pciexpress.html.
Analyzer Power Management Capabilities
The SPX analyzer provides low power state support on both upstream and downstream bus traffic. Users are provided the ability to specify an electrical idle state as a trigger condition, and can specify that this condition be detected from either the upstream device or downstream device.
Electrical idle and FTS ordered sets may be selected for exclusion from the capture (filtered).
As the device under test exits low power states, it transmits FTS ordered sets. The analyzer very quickly detects this transition from electrical idle and typically captures all but 1 or 2 of the FTS ordered sets transmitted.
Capturing the Electrical Idle Bus Condition
To capture the electrical idle bus condition, the Exclude Idles option needs to be deselected in the capture dialog box. This feature applies to both the analyzer and exerciser. See figure 5 below.
Figure 5. Filter Control for Electrical Idle Bus Condition.
Triggering on an Electrical Idle Bus condition
To trigger the SPX analyzer or exerciser on an electrical idle, access the Trigger On menu and open the Other Triggers selection. See figure 6 below.
Figure 6. Electrical Idle Trigger Selection.
Display of Electrical Idle in Capture View
The electrical idle bus event is captured and displayed in the Catalyst trace display. An example of an electrical idle bus event is shown below in figure 7.
Note that the electrical idle event is characterized for duration. It is also preceded by an electrical idle ordered set, and succeeded by FTS ordered sets.
Figure 7. Electrical Idle Displayed in Packet Capture View.
Electrical Idle Filtering Options
The specification calls for very stringent requirements relating to the timing relationship between electrical idle ordered sets and the electrical idle state. Per specification, the transmitter driver asserts an electrical idle bus condition no more than 8ns after an electrical idle ordered set is transmitted (see the specification for important details).
The SPX exerciser has been designed to drive the electrical idle bus condition after transmission of an electrical idle ordered set in under 2ns. Typically, these values are between 300ps and 1.2ns. The diagram below illustrates this timing relationship.
Figure 9. Timing Relationship between Electrical Idle Ordered Set and Electrical Idle
ASPM-Related Registers
The PCI Express Link Capabilities Register for each PCI Express device installed on a system indicates support levels for ASPM states. Bits 11-10b in this register are specific to ASPM. See table 3 below.
|
Bits 11-10 Values |
APSM Support |
|
00b |
Reserved |
|
01b |
L0s Supported |
|
10b |
Reserved |
|
11b |
L0s and L1 Supported |
|
|
|
Table 3. ASPM Values in Link Capabilities Register
The PCI Express Link Control Register for each PCI Express device installed on a system is accessible by system software. Bits 01-00b in this register are specific to APSM and are used for enabling/disabling ASPM support. See table 4 below.
|
Bits 01-00 Values |
ASPM Status |
|
|
|
L0s |
L1 |
|
00b |
Disabled |
Disabled |
|
01b |
Enabled |
Disabled |
|
10b |
Disabled |
Enabled |
|
11b |
Enabled |
Enabled |
|
|
|
|
Table 4. ASPM Status Values in Link Control Register.
Register Access in Non-System Development Platform Environment
In testing a device using the Catalyst SPX exerciser in the PXP-100 development platform environment (see figure 2 above), these registers are directly accessible using appropriate CFG RD and CFG WR commands issued by the exerciser. The SPX application software will decode and display configuration space registers in a formatted table as shown in figure 10 below. Note that this configuration decode table is also available when running the SPX in-system, as an analyzer.
Figure 10. SPX Configuration Decode Table (Link Control Register Highlighted).
Register Access In-System
While the SPX exerciser can be installed onto a PCI Express system slot as an emulated endpoint device, it will be prevented from accessing system registers by the upstream device, which will reject any configuration space access attempts (as required by the specification). Catalyst provides a specialty software utility that can be installed on the PCI Express system that will provide easy read/write access to all PCI and PCI Express configuration.
To obtain a no-cost copy of this software utility, please contact Catalyst at support@getcatalyst.com, visit our website at www.getcatalyst.com, or call us at (408) 365-3846.
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